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S.V. Gavrilov, G.A. Pirutina, A.N. Schelokov
THE INTERVAL DELAY AND TRANSITION TIME ESTIMATION METHOD OF NANOMETER CMOS LIBRARY CELLS
A wide set of digital circuit simulation problems requires both maximal node delay and minimal delay. The accurate minimal delay model depends on glitches and simultaneous gate input switching. But the existing logic level performance analysis tools, as a rule, use simplified pin-to-pin- gate delay model. This paper describes the method, which provides considerable logic level interval delay analysis accuracy versus the famous approaches accounting for the simultaneous multiple input switching.
Static timing analysis; gate delay; IP-block.
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..., . . .
- ( ); e -mail: sergey.v.gavrilov@ippm.ru; 124365, , , . , 3; .: 84997299890; ; . .
- e -mail: pirutina_g@ippm.ru; ; ...
- e-mail: schan@ippm.ru; .: 84997299845; . .
Gavrilov Sergey Vitalievich - The Institute for Design Problems in Microelectronics of the Russian Academy of Science; e-mail: sergey.v.gavrilov@ippm.ru; 3, Sovetskaya street, Zelenograd, 124681, Russia; phone: +74997299890; the department of digital design automation; head the department.
Pirutina Galina Aleksandrovna - e-mail: pirutina_g@ippm.ru; the department of digital design automation; junior researcher.
Schelokov Albert Nikolaevich - e-mail: schan@ippm.ru; phone: +74997299845; deputy director.